Traditionally, CMOS operational amplifiers (opamps) apply cascoding techniques to ensure an acceptable gain with the minimum number of gain stages. The use of cascoding transistors, however, fundamentally limits the lowest supply voltage of a CMOS opamp. Considering that only one saturation voltage V.sub.Dsat (e.g., a current source) suffices to drive the output transistor, the minimum supply voltage of CMOS opamp circuits can be reduced to V.sub.GS +V.sub.Dsat. To obtain this minimum level no cascodes or differential stages can be used in the circuit to drive the output stage. The elimination of cascodes and differential stages to drive the output transistor poses severe demands on the frequency compensation of the amplifier.
Lowering the threshold voltage of the MOS process does not lead to a lower minimum supply voltage of the cascode circuits when a cascode is used between the gate and source of a transistor. To illustrate this, FIG. 1 shows a simplified schematic of a conventional opamp with a push-pull output stage. This is described in Bababezhad, J. N., `A Low-Output-Impedance Fully Differential Op Amp with Large Output Swing and Continuous-Time Common-Mode Feedback`, IEEE Journal of Solid State Circuits, vol. 26, no. 12, December 1991, whose contents are herein incorporated by reference. The circuit consists of an input differential pair M30/M35 and output stage M10/M20 separated by cascode transistors M21 and M24. The bold lines in FIG. 1 indicate the places where two stacked drain-source voltages are connected between the gate and the source of an output transistor. When the gate-source voltages of the output transistors drop below the summed saturation voltages of cascode transistors M11 plus M12 and M21 plus M22, the gain of the circuit drastically reduces.
This effect, which will render an important class of opamp circuits useless in the near future, is caused by the independence of the saturation voltage V.sub.Dsat of a MOS device from the threshold voltage V.sub.th. ##EQU1##
To accommodate the two stacked drain-source voltages V.sub.DS of the cascodes M11/M12 and M21/M22, the W/L ratios of the cascode transistors have to be chosen high, as indicated by equation (1), and the W/L ratio of the output transistors low. The large cascode transistors increase the die area of the silicon chip, while the low W/L of the output transistors results in a large V.sub.GS and thus a high minimum supply voltage. In next generation CMOS processes, with lower threshold voltages, it will become even more critical, i.e., more difficult, to fit two stacked drain-source voltages into the gate-source voltage of an output transistor.
Also, CMOS amplifiers containing a differential gain stage to drive the output transistor suffer from restrictions similar to those of the cascode circuits. FIG. 2 shows an opamp with four cascaded gain stages and nested Miller compensation, described in Huijsing, J. H., `Multi-stage amplifier with capacitive nesting for frequency compensation`, U.S. Pat. No. 4,559,502, whose contents are herein incorporated by reference. In the circuit of that patent, to accomplish a correct sign for the Miller loops, the two intermediate stages, M30 and M40 are implemented as differential pairs. The bold lines in FIG. 2 reveal the voltage loop with two stacked saturation voltages between the gate and source of output transistor M20.